System-level performance gains in the forms of single- thread performance, throughput, and power efficiency have historically been fueled by performance, density, and power improvements by scaling device and on-chip interconnects. However, silicon economics and the limits of reticle size are driving a disruption, requiring HPC and AI hardware designers to look at new ways of designing chips and considering new architectures. Chiplet integration technologies offer a modular approach to continued performance scaling by providing enhanced functionality and improved operating characteristics. Instead of fabricating a single large multicore CPU die, smaller dies can be arranged within a package with very short chip to chip connections at the same performance. The smaller dies have higher yields, and if integration cost is reasonable, the overall solution then scales economically. Custom chips can then be made, with the flexibility to combine chips of different technology nodes for a specific application or workload. This talk will focus on key chiplet integration technologies that are gaining traction in the industry and are driving this chiplet revolution.