IEEE Electron Device Letters

InAs-Si nanowire heterojunction tunnel FETs

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In this letter, we present vertical InAs-Si nanowire heterojunction tunnel FETs (TFETs). The devices consist of an InAs source on a Si channel and drain, with a wraparound gate stack. The Si-InAs combination allows achieving high $I-{\rm on}/I \rm off ratios above 10 6, with an $I \rm on of 2.4 $\mu\hbox{A}/\mu\hbox{m}$ and an inverse subthreshold slope of 150 mV/dec measured over three decades of current. Ni alloying of the InAs top contact is shown to improve performance of both diodes and TFETs significantly. The combination of higher doping at the contact and the alloying also leads to an enhanced performance compared with previously published devices. © 2012 IEEE.