Strong and flexible domain typing for dynamic E-business
Yigal Hoffner, Simon Field, et al.
EDOC 2004
Sparse-matrix vector multiplication is an important kernel that often runs inefficiently on superscalar RISC processors. This paper describes techniques that increase instruction-level parallelism and improve performance. The techniques include reordering to reduce cache misses (originally due to Das et al.), blocking to reduce load instructions, and prefetching to prevent multiple load-store units from stalling simultaneously. The techniques improve performance from about 40 MFLOPS (on a well-ordered matrix) to more than 100 MFLOPS on a 266-MFLOPS machine. The techniques are applicable to other superscalar RISC processors as well, and have improved performance on a Sun UltraSPARC™ I workstation, for example.
Yigal Hoffner, Simon Field, et al.
EDOC 2004
G. Ramalingam
Theoretical Computer Science
Thomas R. Puzak, A. Hartstein, et al.
CF 2007
Xiaozhu Kang, Hui Zhang, et al.
ICWS 2008