A calibrated delay line is a key component in many modern digital systems. Traditionally, these lines are designed as real-time pipelines with static granularity, fine enough to handle a worst case input rate. However, due to their rigid structure, they have suboptimal energy for low-and varying-rate input streams. We introduce a complete methodology for designing reconfigurable delay lines that dynamically adapt their granularity to actual input traffic, on-the-fly, without stalling or disturbing normal operation. Two or more modes can be used, with different granularities to handle different traffic densities. During sparser traffic, the system is reconfigured to the proper coarser-grain mode, thereby reducing total energy, and it reverts to fine-grain mode during denser traffic. In each case, overall delay is preserved. This strategy is especially beneficial for applications where input traffic is highly varied. The particular focus of this paper is one promising domain, continuous-time digital signal processors (CT DSPs), a new class of processors targeting low-energy applications. The proposed system includes two lightweight asynchronous control blocks: a digital controller to continuously monitor input traffic, and a micropipeline to dynamically reconfigure the entire delay line. Design approaches for bimodal and trimodal adaptive lines are presented, which are then implemented in a 0.13-μ m IBM CMOS technology. Simulations for these delay lines demonstrate savings in overall dynamic power up to 45.5% and 71.1%, respectively, when compared with a nonadaptive design, with only minimal area overhead (1.5% and 3%, respectively, for a targeted configuration). Using extensions to more configuration modes, further power reductions can be achieved. While results are presented for CT DSPs, significant benefits are also expected in many other domains, where the delay lines are used.