Kristof Tahy, Siyuranga Koswatta, et al.
DRC 2009
Investigation of gate-induced drain leakage (GIDL) in thick-oxide dual-gate doped-and undoped-channel FinFET devices through 3-D process and device simulations is presented. For a given gate length (LG) and gate dielectric thickness, the placement and grading of the drain junction and the channel doping are shown to have a tremendous impact on GIDL. Suppression of GIDL by as much as two orders of magnitude can be realized by formation of steep underlapped junctions for both doped-and undoped-channel devices. The prospect of low leakage levels in doped-channel high-VT FinFETs makes them suitable for memory cell applications. © 2012 IEEE.
Kristof Tahy, Siyuranga Koswatta, et al.
DRC 2009
Jun Yuan, C. Gruensfelder, et al.
ICSICT 2010
Darsen Lu, Pierre Morin, et al.
ECSSMEQ 2014
Rajiv V. Joshi, Keunwoo Kim, et al.
IEEE Transactions on VLSI Systems