A routing scheme is described for communication in a multiprocessor system employing a unique-path multistage interconnection network in the presence of faults in the network. The scheme avoids faulty elements by routing the message to an incorrect destination and then making an extra pass to route to the correct destination. It is capable of tolerating all single faults and many multiple faults in all except the first and last stages of the network. The routing scheme is useful for tolerating both permanent as well as intermittent faults in the network. It is transparent to the processors in the system which eliminates the need for elaborate reconfiguration protocols. The hardware overhead for implementing the scheme is very small and no time-penalty is paid in the fault-free case. © 1989.