Over the past decade, CMOS technology has been continuously scaled down to satisfy the demand for enhanced performance and higher density. As a result, the importance of electron beam lithography utilized as a direct writing technique for sub-micron geometries has increased significantly. Although the application of electron beam lithography encompasses both the micron and sub-micron regimes, a more recent trend is directed towards a strategy of mixing photo-optical and electron beam technologies. The goal is to improve throughput and reduce overall cost of fabricating high density VLSI device geometries without compromising device performance. This is readilly achieved by writing only selected critical levels with high resolution electron beam techniques and all other levels with high throughout optical methods. The results of the successful combination of the lithographic capabilities of the GCA MANN 6300 10X optical stepper and the 0.5 micron IBM EL-3 variable shaped electron beam tools to fabricate functional, partially scaled N- and P- channel CMOS devices with 0.5 micron effective gate lengths are presented. The lithography related factors which influence overlay, pattern quality, and performance are discussed. © 1986.