Design considerations for 50G+ backplane linksThomas ToiflMatthias Braendliet al.2016ESSCIRC 2016Conference paper
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOSHazar YuekselMatthias Braendliet al.2016ESSCIRC 2016Conference paper
Experimental demonstration of a nanoelectromechanical switch-based logic library including sequential and combinational gatesChristopher L. AyalaAntonios Bazigoset al.2016ESSCIRC 2016Conference paper