Design considerations for 50G+ backplane links
- Thomas Toifl
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
Conference paper
Publications
3 results at ESSCIRC 2016
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS
- Hazar Yueksel
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
Conference paperExperimental demonstration of a nanoelectromechanical switch-based logic library including sequential and combinational gates
- Christopher L. Ayala
- Antonios Bazigos
- et al.
- 2016
- ESSCIRC 2016
Conference paper