Solid-State Electronics

Current transport across a grain boundary in polycrystalline semiconductors

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A unified approach to current transport across a grain boundary in polycrystalline semiconductors is developed. The resulting expressions for potential barrier and J-V characteristics are of general validity, in contrast to the many derivations of previous models, each with its own conditions of validity. The study concentrates on the carrier-trapping effect, and the trapping-state density can be monoenergetic, continuous, gaussian, or any reasonable distribution. By solving Possion's equation under suitable boundary conditions without the depletion approximation, a single formulation is obtained for potential barriers in two adjacent grains with different sizes and doping levels. The grain-boundary scattering effect is approximated as a rectangular potential barrier. The voltage division of an applied bias across the junction is determined under the current-continuity conditions. A single expression with suitable computational simplicity is then presented for the J-V characteristics across the many-valley semiconductor/grain-boundary/semiconductor junction. It uses the generalized WKB approximation and Fermi-Dirac statistics, and also considers the ellipsoidal energy surfaces of different valleys. All the thermionic, thermionic-field, and field emissions are included. As a result, the approach is valid for many-balley semiconductor materials over a wide range of temperatures, trapping-state density distributions, doping concentrations, grain sizes, and crystalline orientations. © 1983.


01 Jan 1983


Solid-State Electronics