Performance measurement and data base design
Alfonso P. Cardenas, Larry F. Bowman, et al.
ACM Annual Conference 1975
The purpose of this paper is to study reducibilities that can be computed by combinational logic networks of polynomial size and constant depth containing ANDs, ORs and NOTs, with no bound placed on the fan-in of AND-gates and OR-gates. Two such reducibilities are defined, and reductions and equivalences among several common problems such as parity, sorting, integer multiplication, graph connectivity, bipartite matching and network flow are given. Certain problems are shown to be complete, with respect to these reducibilities, in the complexity classes deterministic logarithmic space, nondeterministic logarithmic space, and deterministic polynomial time. New upper bounds on the size-depth (unbounded fan-in) circuit complexity of symmetric Boolean function are established.
Alfonso P. Cardenas, Larry F. Bowman, et al.
ACM Annual Conference 1975
Yigal Hoffner, Simon Field, et al.
EDOC 2004
Limin Hu
IEEE/ACM Transactions on Networking
Gal Badishi, Idit Keidar, et al.
IEEE TDSC