CMOS platform for atomic-scale device fabrication

Abstract

Controlled atomic scale fabrication based on scanning probe patterning or surface assembly typically involves a complex process flow, stringent requirements for an ultra-high vacuum environment, long fabrication times and, consequently, limited throughput and device yield. We demonstrate a device platform that overcomes these limitations by integrating scanning-probe based dopant device fabrication with a CMOS-compatible process flow. Silicon on insulator substrates are used featuring a reconstructed Si(001):H surface that is protected by a capping chip and has pre-implanted contacts ready for scanning tunneling microscope (STM) patterning. Processing in ultra-high vacuum is thereby reduced to a few critical steps. Subsequent reintegration of the samples into the CMOS process flow opens the door to successful application of STM fabricated dopant devices in more complex device architectures. Full functionality of this approach is demonstrated with magnetotransport measurements on degenerately doped STM patterned Si:P nanowires up to room temperature.