FPGA-based coprocessor for text string extraction
N.K. Ratha, A.K. Jain, et al.
Workshop CAMP 2000
The high-speed cache memory acts as a buffer between main memory and the central processing unit (CPU). Cache design, a direct-mapped cache and a fully associative cache and its implementation can make or break the performance (cache size, associativity, line size, physical versus virtual, and degree of asynchrony) of a computer systems. Accordingly, a higher level of associativity is better with respect to caches and physically addressed caches are better for environments where context switching is very frequent. In designing or tuning a CPU intensive application, it is advisable to maximize locality and avoid memory-access sequences that increase by large powers of 2.
N.K. Ratha, A.K. Jain, et al.
Workshop CAMP 2000
Limin Hu
IEEE/ACM Transactions on Networking
Yao Qi, Raja Das, et al.
ISSTA 2009
Khalid Abdulla, Andrew Wirth, et al.
ICIAfS 2014