John M. Boyer, Charles F. Wiecha
DocEng 2009
The high-speed cache memory acts as a buffer between main memory and the central processing unit (CPU). Cache design, a direct-mapped cache and a fully associative cache and its implementation can make or break the performance (cache size, associativity, line size, physical versus virtual, and degree of asynchrony) of a computer systems. Accordingly, a higher level of associativity is better with respect to caches and physically addressed caches are better for environments where context switching is very frequent. In designing or tuning a CPU intensive application, it is advisable to maximize locality and avoid memory-access sequences that increase by large powers of 2.
John M. Boyer, Charles F. Wiecha
DocEng 2009
Michael Ray, Yves C. Martin
Proceedings of SPIE - The International Society for Optical Engineering
Raymond Wu, Jie Lu
ITA Conference 2007
M.J. Slattery, Joan L. Mitchell
IBM J. Res. Dev