APS March Meeting 2023

Better Than Worst-Case Decoding for Quantum Error Correction

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The overheads of classical decoding for quantum error correction grow rapidly with the number of logical qubits and their code distance. Decoding at room temperature is bottle-necked by refrigerator I/O bandwidth while cryogenic on-chip decoding is limited by area/power/thermal budget. To overcome these overheads, we are motivated by the observation that the common case error signatures are fairly trivial with high redundancy / sparsity. If suitably exploited, these trivial signatures can be decoded and corrected with insignificant overhead, alleviating the above bottlenecks, while still handling worst-case complex signatures by state-of-the-art means. Our proposal, targeting Surface Codes, consists of: 1) A lightweight decoder for decoding and correcting trivial common-case errors, designed for the cryogenic domain. The decoder is implemented for SFQ logic. 2) A statistical confidence-based technique for off-chip decoding bandwidth allocation, to efficiently handle rare complex decodes which are not covered by the on-chip decoder. 3) A method for stalling circuit execution, for the worst-case scenarios in which the provisioned off-chip bandwidth is insufficient to complete all requested off-chip decodes. In all, our proposal enables 70-99+% off-chip bandwidth elimination across a range of error rates, while achieving a 15-37x resource overhead reduction compared to prior on-chip-only decoding.