About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Conference paper
Architecture and design of a pseudo two-port VLSI snoopy cache memory
Abstract
A CMOS VLSI cache memory subsystem that includes a 72K-bit cache memory, an 11K-bit tag memory, a 1.3K-bit state array, two special buffers and cache control logic, has been designed and integrated on a microprocessor chip. The architecture, design and analysis of the cache design are presented. The design achieves higher system performance by reducing the cache reload penalty through a pseudo-two-port architecture which utilizes a reload buffer and a store-back buffer. It also maintains cache data coherency and supports multiprocessing by bus snooping. A single-port tag is used for concurrent snooping and CPU access with an enhanced write-once protocol. A cost-effective 'locked replacement' scheme was incorporated to maintain data coherency in these two special buffers. Cache modeling and analysis were carried out to derive the proper design point.
Related
Conference paper