Over the past several years, CMOS technology has been continuously driven to achieve enhanced performance and higher density. The resulting reduction in semiconductor dimensions has surpassed the limits attainable by the most advanced optical lithography tools. As a result, the utilization of electron beam lithography direct writing techniques to satisfy VLSI patterning requirements has increased significantly. The ability to write patterns at high resolution, however, is by itself insufficient to accomplish the fabrication of VLSI device structures at sub-micron ground rules. The successful application of sub-micron scaling principles to device fabrication requires the complete integration of tool capability and resist process control. In order to achieve the realization of improved CMOS device performance and circuit density, sub-micron ground rules (line width control and overlay) must be satisfied over the full chip. This paper reports on a high performance, fully scaled 0.5μm CMOS technology in which each circuit level is patterned using a modified IBM EL-3  variable shaped electron beam direct write tool. Significant gains in both density and performance at reduced power supply levels (3.3 volts) are obtained over previously reported 1.0μm (5.0 volt) CMOS technology . The details of the innovative, integrated lithography strategy used for this application and the lithography related factors which influence overlay, pattern quality, and device performance will be presented. The modified EL-3 variable shaped electron beam system which was utilized to develop the 0.5μm CMOS technology reported in this paper has been further enhanced to achieve 0.25μm performance capability for both direct write and mask writing applications . Overlay accuracy has been improved through the implementation of low noise electronics and electron optical column design improvements. The application of a 0.25μm variable shaped beam performance capability to the further scaling down of device geometries to the sub-half micron regime and the impact on the integrated lithography process at these reduced dimensions will be discussed. © 1989.