About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
International Conference on APL 1982
Conference paper
APL on a multiprocessor architecture
Abstract
Several computers have been built experimentally which incorporate a large number of identical CPUs. One example known to this author contains 65 identical microprocessors: one is the "master" and issues orders (normally identical or nearly so) to the other 64, called "slaves". The master and each slave has its own storage unit. It is proposed that such a computer could be used as an auxiliary to a conventional computer to assist in the execution of APL code. APL vectors would be stored in scattered fashion, one element per slave memory, so that they can be processed in parallel. Reduce and scan operations are considered in detail, and requirements are derived for the data interconnection paths among the processors.