Analysis of a single-electron decimal adder

Abstract

In this letter, a decimal adder using single electron transistors as a building block is presented. The design is described and the equivalent circuit is extracted, from which the dc performance of the adder is derived. This simple analytical approach is found to be in good agreement with numerical simulation. A detailed sensitivity analysis is performed where the effects of temperature, capacitance, conductance, and background-charge variations are analyzed and the attendant change in device performance is described. This adder needs a number of wires four times less than binary adders and hence alleviates the interconnections problem present in high density circuits. © 1997 American Institute of Physics.