An 18 ns 56-bit multiply-adder circuit

Abstract

A multiply-adder that achieves a 56-b X × Y + Z function with cycle time of 18 ns in a 1-μm CMOS technology is discussed. The organization requires only two pipeline stages, ensuring quick recovery from branch instructions. The design is for the fraction part of a 64-b multiply-adder and is itself 56 b wide at input and output. To achieve high performance and reasonable density, it uses Booth encoding and a Wallace tree array. Data are captured at the input latches and routed immediately to the Booth encoders, which, in addition to encoding the X input, also provide driven Y and Y-bar signals for the array. The Z input is also captured and routed to the Z shifter. Encoded X, Y-bar, and Z and shifted Z signals are all routed to the partial product array. Booth encoding for 56 b produces 29 partial products; the Z input raises the number of terms to be added to 30. The partial product array reduces this to three, at which point a second latch captures the reduced result. After the latch, the three terms are reduced to two in a full adder, and the resulting two terms added and renormalized. The partial produce array uses 7-to-3 compressors in most places. This simplifies the tree wiring and provides three extra inputs which can be used for rounding, the twenty-ninth partial product from the Booth encoding, and a shifted Z input, thus computing X × Y + Z with almost the same amount of hardware required for X × Y.