Effectiveness of using supply voltage as back-gate bias in ground plane SOI MOSFET's

Abstract

A study, which demonstrated that Ground Plane (GP)-SOI devices are optimal for the digital body biasing (DBB) technique, was presented. GP SOI MOSFET was shown to have advantages over bulk devices, such as better controllability of V t, and the absence of p-n junctions, which alleviates the issues related to forward-biased junction currents for swapped back biases. It was shown that GP-SOI MOSFET's were optimal for the DBB scheme offering high on-current and low design complexity without having power/performance issues related to the forward-biased p-n junction current in bulk CMOS. The result also shows that GP-SOI can deliver same performance as DG-SOI at 90X lower standby leakage by dynamically switching the back-gate bias.