220 mm² 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architecture

Abstract

A 220 mm2 256 Mb SDRAM that uses single-sided stitched-wordline architecture, a shared row decoder with asymmetric block activation, an intra-unit address increment pipeline scheme, single-ended read-write drive, and selectable row domain and divided column redundancy is presented. This chip contains 8 32 Mb double units. Either the left or the right 16 Mb unit in each selected 32 Mb double unit is further decoded. A 4 bank SDRAM is realized by assigning 13 row addresses with 2 bank addresses. Two sets of 16 DQs and 16 read-write lines are arranged on the left and right chip halves.