Functional Testing of AI Cores through Thinned 3D I/O Buffer Dies in 3D Die-Stacked Modules
- Mukta Farooq
- Arvind Kumar
- et al.
- 2022
- ECTC 2022
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52 results for Chiplets
Copper Content Optimization for Warpage Minimization of Substrates with an Asymmetric Cross-Section by Genetic Algorithm
- Hiroyuki Mori
- Sayuri Kohara
- 2021
- ECTC 2021
Plasma Activated Low-temperature Die-level Direct Bonding with Advanced Wafer Dicing Technologies for 3D Heterogeneous Integration
- Katsuyuki Sakuma
- Dishit Parekh
- et al.
- 2021
- ECTC 2021
3D Die-Stack on Substrate (3D-DSS) Packaging Technology and FEM Analysis for 55um-75um Mixed Pitch Interconnections on High Density Laminate
- Katsuyuki Sakuma
- Mukta Farooq
- et al.
- 2021
- ECTC 2021
Plating-free Bumping by Cu Nanopaste and Injection Molded Solder (IMS) for Fine Pitch Flip Chip Joining
- Toyohiro Aoki
- Eiji Nakamura
- et al.
- 2020
- ECTC 2020
Proposal of Package Structure Requirements for Effective Cooling from the Bottom Side of Chips (from the Substrate Side), Aiming for a Three-Dimensional (3D) Chip Stack
- Keiji Matsumoto
- Hiroyuki Mori
- 2016
- ECTC 2016
D2W and W2W Hybrid bonding system with below 2.5 micron pitch for 3D chiplet AI applications
- Katsuyuki Sakuma
- Roy Yu
- et al.
- 2024
- IEDM 2024
Design of Analog-AI Hardware Accelerators for Transformer-based Language Models (Invited)
- Geoffrey Burr
- Sidney Tsai
- et al.
- 2023
- IEDM 2023
Optical Communication and Energy Conversion for Small-Footprint Edge Computing
- Ning Li
- 2020
- MRS Spring/Fall Meeting 2020
Artificial Intelligence (AI) based methodology to minimize asymmetric bare substrate warpage
- Sathya Raghavan
- Hiroyuki Mori
- et al.
- 2023
- ECTC 2023