On the Path to AI hardware via Chiplet Integration Enabled by High Density Organic Substrates

Abstract

Even though circuit elements are still scaling, performance scaling no longer follows Moore’s Law. Instead of fabricating a single large multicore CPU die, smaller dies can be arranged within a package with very short chip-chip connections at the same performance. The smaller dies have higher yields, and if integration cost is reasonable, the overall solution then scales economically. The availability of low-latency, low energy per bit, and high-bandwidth connections to memory is a necessary condition to realize the performance potential of these compute engines. In this study, the heterogeneous integration of three mixed test chips is investigated. An HBM2 test die, a die with a 75/55 um mixed micro-bump solder joint pitch, and a smaller die at 150um solder joint pitch are all joined onto an organic substrate at 2 m/2 m line and space to achieve high-bandwidth interconnections. We confirmed our join quality by performing cross-sectional analysis, 3D X-ray of the interconnect, and electrical testing. Selective cross-sectional analysis was used to study the geometry of micro-bumps after the chip join, and it was confirmed that micro-bumps were joined without defects, even at different pitches within the same die. More details and results of the organic substrate designed for AI hardware and the newly developed advanced TCB-based bonding method, special underfill technology will be discussed in this paper. Novel circuit designs, characterization, and reliability of these high-density substrates were also evaluated. New substrate design groundrules are proposed to meet JEDEC reliability requirements that can enable an AI hardware prototype. A complementary non-linear finite element analysis is performed to further characterize and design the allowable critical via configurations of the high-density substrate and of the critical solder joints subjected to aggressive thermal cycling testing.