A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid cu-adhesive bonding
- F. Liu
- R.R. Yu
- et al.
- 2008
- IEDM 2008
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28 results for Robert Wisnieff
Interconnect Issues post 45nm
- S.M. Rossnagel
- Robert L. Wisnieff
- et al.
- 2005
- IEDM 2005
High-dielectric constant insulators and the AMLCD process: is amorphous BST a candidate?
- P. Andry
- D.A. Neumayer
- et al.
- 1999
- MRS Spring Meeting 1999
Electrical test sites for AMLCD-TFT array process characterization
- E.G. Colgan
- R.J. Polastre
- et al.
- 1998
- MRS Spring Meeting 1998
Interconnect material choices for future scaled devices
- Gregory Fritz
- Adam Pyzyna
- et al.
- 2012
- ADMETA 2012
Extending photo-patternable low-κ concept to 193 nm lithography and e-beam lithography
- Qinghuang Lin
- Alshakim Nelson
- et al.
- 2011
- SPIE Advanced Lithography 2011
Patternable low-κ material for "greener" semiconductor manufacturing
- Qinghuang Lin
- Shyng-Tsong Chen
- et al.
- 2010
- ICSICT 2010
Multi-level integration of patternable low-κ material into advanced Cu BEOL
- Qinghuang Lin
- Shyng-Tsong Chen
- et al.
- 2010
- Proceedings of SPIE - The International Society for Optical Engineering 2010
Material and process for advanced Cu/ULK integration
- Chih-Chao Yang
- Daniel C. Edelstein
- et al.
- 2008
- ADMETA 2008
Integration and reliability of CVD Ru Cap for Cu/Low-k development
- C.-C. Yang
- D. Edelstein
- et al.
- 2009
- IITC 2009