Deep learning acceleration in 14nm CMOS compatible ReRAM array: device, material and algorithm co-optimization
- N. Gong
- Malte J. Rasch
- et al.
- 2022
- IEDM 2022
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12 results for C. S. Wajda
Resistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning
- Youngseok Kim
- Soon-Cheon Seo
- et al.
- 2021
- IEEE Electron Device Letters
Hardware Algorithm Co-optimization on Resistive RAM Cross-bar Array for Scalable Analog Compute Technology for AI application
- Y. Kim
- S.-C. Seo
- et al.
- 2021
- SNW 2021
Process-Induced ReRAM Performance Improvement of Atomic Layer Deposited HfO2 for Analog In-Memory Computing Applications
- Steven Consiglio
- H. Higuchi
- et al.
- 2021
- IMCS 2021
Higher-K formation in atomic layer deposited Hf1-xAlxOy
- Kandabara Tapily
- Steven Consiglio
- et al.
- 2014
- ECSSMEQ 2014
Optimizing band-edge high-κ/metal gate n-MOSFETs with ALD lanthanum oxide cap layers-oxidant and positioning effects
- Robert D. Clark
- H. Jagannathan
- et al.
- 2010
- ECS Transactions
Engineering band-edge high-κ/metal gate n-MOSFETs with cap layers containing group IIA and IIIB elements by atomic layer deposition
- H. Jagannathan
- L.F. Edge
- et al.
- 2009
- ECS Meeting 2009
High-K gate dielectric structures by atomic layer deposition for the 32nm and beyond nodes
- R.D. Clark
- S. Consiglio
- et al.
- 2008
- ECS Meeting 2008
Process and electrical characteristics of MO-ALD HfO2 films for high-K gate applications grown in a production-worthy 300 mm deposition system
- R.D. Clark
- C.S. Wajda
- et al.
- 2007
- ECS Meeting 2007
Dual work function metal gate CMOS using CVD metal electrodes
- V. Narayanan
- A.C. Callegari
- et al.
- 2004
- VLSI Technology 2004