An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2012
- VLSI Circuits 2012
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45 results for Jose A. Tierno
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation
- Sameh Asaad
- Ralph Bellofatto
- et al.
- 2012
- FPGA 2012
Indirect phase noise sensing for self-healing voltage controlled oscillators
- S. Yaldiz
- V. Calayir
- et al.
- 2011
- CICC 2011
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
- Jae-Sun Seo
- Bernard Brezzo
- et al.
- 2011
- CICC 2011
A DPLL-based per core variable frequency clock generator for an eight-core POWER7™ microprocessor
- Jose Tierno
- Alexander Rylyakov
- et al.
- 2010
- VLSI Circuits 2010
A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI
- Alexander Rylyakov
- Jose Tierno
- et al.
- 2008
- CICC 2008
Characterization of equalized 10-Gb/s multimode fibre LAN links using transverse 7-tap analog FIR filter in 0.13-μm CMOS
- Aleksandar Risteski
- Scott Reynolds
- et al.
- 2005
- ECOC 2005
DMD characterization of legacy multimode fibers at 1300nm for link equalization purposes
- Petar Pepeljugoski
- Aleksandar Risteski
- et al.
- 2004
- LEOS 2004
Bringing optics inside the box: Recent progress and future trends
- J.A. Kash
- C.W. Baks
- et al.
- 2003
- LEOS 2003
Improved Performance of 10 Gb/s Multimode Fiber Optic Links Using Equalization
- P. Pepeljugoski
- J. Schaub
- et al.
- 2003
- OFC 2003