Characterization and mitigation of overlay error on silicon wafers with nonuniform stress
- T.A. Brunner
- V. Menon
- et al.
- 2014
- SPIE Advanced Lithography 2014
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22 results for Michael Belyansky
High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
Performance elements for 28nm gate length bulk devices with gate first high-k metal gate
- Jun Yuan
- C. Gruensfelder
- et al.
- 2010
- ICSICT 2010
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009
Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing
- M. Cai
- B. Greene
- et al.
- 2008
- IEEE International SOI Conference 2008
SMT and enhanced SPT with Recessed SD to improve CMOS Device Performance
- S. Fang
- S.S. Tan
- et al.
- 2008
- ICSICT 2008
Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- X. Chen
- S. Fang
- et al.
- 2006
- VLSI Technology 2006
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
Study of alternate hardmasks for extreme ultraviolet patterning
- Anuja De Silva
- Indira Seshadri
- et al.
- 2016
- JVSTB
Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress
- Timothy A. Brunner
- Vinayan C. Menon
- et al.
- 2013
- Journal of Micro/Nanolithography, MEMS, and MOEMS