Backside Routing Enablement Considerations For Advanced Node GAA Devices

Backside routing is an innovative feature offered by several foundries in 3nm and beyond nodes. In this paper, we will discuss the considerations for digital design implementation to use the backside layers most efficiently for maximizing PPA (Power Performance Area) as shown in Fig 1 & 2. The considerations involve choosing the right strategies for technology definition and implementation flow for power, clock and specific signals that can benefit from backside routing.