Publications

20 results for D.C. La Tulipe

Upside-down FETS
- - D.C. La Tulipe Jr.
  - D.J. Frank
  - et al.
- 2008
- IEEE International SOI Conference 2008
Wafer-level 3D integration technology
- - Steven J. Koester
  - Albert M. Young
  - et al.
- 2008
- IBM J. Res. Dev
Critical aspects of layer transfer and alignment tolerances for 3D integration processes
- - D.C. La Tulipe
  - L.T. Shi
  - et al.
- 2006
- GBC 2006
Three-dimensional integrated circuits
- - Anna W. Topol
  - Douglas C. La Tulipe Jr.
  - et al.
- 2006
- IBM J. Res. Dev
Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO₂/metal stacks
- - V. Narayanan
  - K. Maitra
  - et al.
- 2006
- IEEE Electron Device Letters
Assembly technology for three dimensional integrated circuits
- - A. Topol
  - D.C. La Tulipe
  - et al.
- 2005
- VMIC 2005
Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs)
- - A. Topol
  - D.C. La Tulipe
  - et al.
- 2005
- IEDM 2005
High resolution 248 nm bilayer resist
- - Q. Lin
  - K.E. Petrillo
  - et al.
- 1999
- SPIE Advances in Resist Technology and Processing 1999
Extension of 248 nm optical lithography: A thin film imaging approach
- - Qinghuang Lin
  - Ahmad D. Katnani
  - et al.
- 1998
- Microlithography 1998
Low energy electron beam top surface image processing using chemically amplified AXT resist
- - C.S. Whelan
  - D.M. Tanenbaum
  - et al.
- 1997
- Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures