Optimization algorithms for energy-efficient data centers
Hendrik F. Hamann
InterPACK 2013
An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed. © Copyright 2008 by International Business Machines Corporation.
Hendrik F. Hamann
InterPACK 2013
A. Gupta, R. Gross, et al.
SPIE Advances in Semiconductors and Superconductors 1990
Corneliu Constantinescu
SPIE Optical Engineering + Applications 2009
Matthias Kaiserswerth
IEEE/ACM Transactions on Networking