Worst-case arbitration time in S-100-type computer bus systems

Abstract

The computer bus systems S-100 and Fastbus use a scheme consisting of extra logic circuits in each device and extra bus lines for arbitrating rapidly between two or more devices seeking to use the bus at the same time. The letter shows how to develop a table of priority numbers that make the arbitration time a maximum, and gives an expression for this maximum time in terms of logic-circuit and bus-propagation delays. © 1982, The Institution of Electrical Engineers. All rights reserved.