Kangguo Cheng, Ali Khakifirooz, et al.
CSTIC 2010
We report high-performance extremely thin SOI MOSFETs fabricated with a channel thickness down to 3.5 nm, sub-20-nm gate length, and contacted gate pitch of 100 nm. At an effective channel length of 18 nm, a drain-induced barrier lowering of 100 mV is achieved by either thinning the channel to 3.5 nm or by applying a reverse back-gate bias to 6-nm channel MOSFETs. Moreover, minimal increase in series resistance is seen when the channel is scaled to 3.5 nm, resulting in no performance degradation with SOI thickness scaling. © 2011 IEEE.
Kangguo Cheng, Ali Khakifirooz, et al.
CSTIC 2010
Lukas Czornomaz, N. Daix, et al.
IEDM 2013
Kangguo Cheng, A. Khakifirooz, et al.
IEEE International SOI Conference 2010
Pouya Hashemi, Karthik Balakrishnan, et al.
VLSI Technology 2014