Publication
JES
Paper

One-Micron Polycide (WSI2 on Poly-Si) MOSFET Technology

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Abstract

An n-channel single level polycide (WSĹ 2 on poly-Si), 22.5 nm gate oxide technology, using electron-beam direct writing for lithography with minimum feature size of 1 μm has been developed to fabricate NMOS circuits. Low resistance (2.7 Ω/) polycide interconnections and small dimension (1 μm) devices are the unique features of this process. The overall process is described in this paper. Polycide deposition, annealing, etching, and oxidation are discussed in detail. Cross sections (0.5K to 2K) of polycide dynamic RAM arrays have been successfully fabricated by this polycide technology. The advantage of using low resistance polycide in integrated circuits is demonstrated. © 1981, The Electrochemical Society, Inc. All rights reserved.

Date

09 Dec 2019

Publication

JES