A fully silicon-integrated restricted Boltzmann machine (RBM) with event-driven contrastive divergence (eCD) algorithm is implemented using novel stochastic leaky integrate-and-fire (LIF) neuron circuits and 6-transistor/2- PCM-resistor (6T2R) unit cells on 90-nm CMOS technology. A bidirectional asynchronous spiking signaling scheme over an analog-weighted phase change memory (PCM) crossbar enables spike-timing-dependent plasticity (STDP) as a local weight update rule. This results in concurrent massively- parallel neuronal computation for low-power on-chip training and inference. Experimental image classification using 100 handwritten digit images from the MNIST database demonstrates 92% training accuracy. SPICE simulation abstracted from the fabricated design indicates 8.95 power. A projection to 28-nm technology gives 5.39 pJ per synaptic operation.