Parameter variations in the transistor characteristics with new materials and process steps pose an increasing challenge for CMOS scaling to nanometer feature size. Alternate channel materials such as silicon-germanium (SiGe) for p-type field effect transistor (pFET) at 32 nm and beyond are useful because of higher mobility and lower threshold voltage (VT) but suffer from higher gate-induced drain leakage (GIDL) and could be a source of additional variability. In this paper, experimental results, a noise-like approach called the statistical impedance field method, and atomistic kinetic Monte Carlo simulations are used to report that the elimination of prehalo Ge preamorphization implant (PAI) from the SiGe pFET process flow reduces GIDL and its variation due to systematic variations in gate length and width but increases the time-zero (static) random GIDL and performance variations. This is primarily due to random dopant position fluctuations in the extension region for off-state leakage (IOFF) variability and in the halo region at the drain sidewall for VT variability. However, the increase in random variability without Ge PAI reduces for lower supply voltages and, thus, offers advantages of reduced GIDL with the same electrostatics, lower systematic variations, and similar I OFF random variability for scaled voltages.