Publication
IEEE T-ED
Paper

Modeling of NBTI kinetics in RMG Si and SiGe FinFETs, Part-I: DC stress and recovery

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Abstract

An ultrafast (10-μs delay) measurement technique is used to characterize the negative bias temperature instability-induced threshold voltage shift (Δ VT) in replacement metal gate-based high-K metal gate Si and SiGe p-FinFETs. The dc stress-recovery Δ VT time kinetics, voltage acceleration factor (VAF), and temperature activation energy (EA) are compared for different germanium percentages (Ge%) in the channel and nitrogen percentages (N%) in the gate-stack. A comprehensive physical model framework based on uncorrelated contributions from the generation of interface (Δ VIT) and bulk oxide (Δ VOT) traps and hole trapping in preexisting defects (Δ VHT) is used to explain the measured data. The impact of Ge% and N% on Δ VT, VAF, EA, temperature (T) dependence of VAF, and stress bias (VGSTR) dependence of EA are quantified. The interface trap generation component is independently verified by direct-current I-V (DCIV) measurements.

Date

01 May 2018

Publication

IEEE T-ED

Authors

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