Publication
VLSI Technology 2017
Conference paper

High performance and record subthreshold swing demonstration in scaled RMG SiGe FinFETs with high-Ge-content channels formed by 3D condensation and a novel gate stack process

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Abstract

We demonstrate scaled high-Ge-content (HGC) strained SiGe pMOS FinFETs with very high short channel (SC) performance using a Replacement High-K/Metal Gate (RMG) flow, for the first time. A novel RMG gate stack process was introduced to create Ge-free interface-layer (IL) with excellent reliability and sub-threshold swing (SS) as low as 62mV/dec, the best reported to date for Si-cap-free SiGe FinFETs. We also present some structural details of the gate stack, for the first time. Short channel characteristics of HGC SiGe FinFETs have also been studied for various fin widths. Compared to our earlier RMG work, improved I/I free process with ultra-thin spacers has led to considerable Ron and Rext reduction. As a result, we have demonstrated very high SiGe performance with Ion=0.45mA/μm at Ioff=100nA/μm at Vdd=0.5V for LG=25nm, matching our record for gate-first SiGe FinFETs and outperforming the gate-first results at such LG.

Date

31 Jul 2017

Publication

VLSI Technology 2017

Authors

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