Publication
IEEE Journal of Solid-State Circuits
Paper

Half-VDD Bit-Line Sensing Scheme in CMOS DRAM's

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Abstract

A sensing scheme in which the bit line is precharged to half VDD is introduced for CMOS DRAM’s. The study shows that the half - VDDbit-line sensing scheme has several unique advantages, especially for highperformance high-density CMOS DRAM’s, when compared to the full- VDDbit-line sensing scheme used for NMOS memory arrays or the grounded bit-line sensing scheme for PMOS arrays in CMOS DRAM’s. © 1984, IEEE.

Date

01 Jan 1984

Publication

IEEE Journal of Solid-State Circuits

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