Publication
IEEE T-ED
Paper

Scaling Limitations of Monolithic Polycrystalline-Silicon Resistors in VLSI Static RAM's and Logic

View publication

Abstract

Quantitative design criteria for monolithic polycrystalline-silicon resistors are established from physical models to develop an optimal device design. Based on the results, the parameters that limit the scaling of polysilicon resistors are identified, and a first-order estimation of minimum device dimensions is projected. The impact of this scaling on the performance of VLSI static RAM’s and logic is analyzed in terms of chip area, power, sensitivity to radiation, rise time, voltage swing, and noise margin. Based on constant-power scaling rules, resistor scaling is limited by the permissible nonlinearity dictated primarily by maximum rise time and sensitivity to radiation. After constant-field scaling, the speed-power product is improved; however, the circuits have less noise margin and voltage swing and become more sensitive to radiation. Copyright © 1982 by The Institute of Electrical and Electronics Engineers, Inc.

Date

01 Jan 1982

Publication

IEEE T-ED

Authors

Share