VLSI Technology 2015
Conference paper

Greater than 2-bits/cell MLC storage for ultra high density phase change memory using a novel sensing scheme

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Multi-level-cell (MLC) is a critical technology to achieve low bit cost for phase change memory. However, resistance drift is an intrinsic material property that kills memory window and imposes formidable challenges for MLC. In this work, we report a radically different sensing concept that exploits the non-linear R-V characteristics of PCM that can easily accommodate 8 resistance levels in three independent 10X sensing windows (100Kω∼1Mω × 3) all on same read speed. Each sensing window only needs to store 2∼3 resistance levels instead of 8 levels needed in conventional MLC method, thus can tolerate resistance drift without closing the memory windows. A maximum of 16 levels of MLC is demonstrated on a 256Mb chip that is suitable for 4-bits/cell application.