FULLY SEALED HALF-MICROMETER NMOS TECHNOLOGY USING DIRECT-WIRE E-BEAM LITHOGRAPHY.

Abstract

Summary form only given. The design, fabrication, and performance of a fully-scaled submicrometer NMOS VLSI technology is demonstrated. In particular, it is shown that although certain nonscaling effects begin to influence the design at this level of miniaturization, none of them is so severe as to limit the feasibility of a 0. 5- mu m technology. Furthermore, improvements in performance and power are still made. The operation of a dynamic RAM array with a cell area of 8. 5 mu m**2 proves the feasibility of high-density dynamic memory built in this scaled technology.