Design guidelines for short, medium, and long on-chip interconnections

Abstract

Short, medium and long on-chip interconnections having line widths of 0.7 - 52 μm are being analyzed in five-metal-layer structures. Design guidelines are formulated for local and global wiring in order to achieve minimum delay and contain crosstalk. The regime when inductive effects are significant is explained and the importance of resistive losses in the power buses is highlighted.