Fully scaled 0.5 micron CMOS technology using variable shaped electron beam lithography

Abstract

Over the past several years, CMOS technology has been continuously driven to achieve enhanced performance and higher density. The resulting reduction in semiconductor dimensions has surpasssed the limits attainable by the most advanced optical lithography tools. As a result, the utilization of electron beam lithography direct writing techniques to satisfy VLSI patterning requirements has increased significantly. In principle, variable shaped electron beam systems are capable of writing linewidths down to at least 0.1 micron. However, the successful application of sub-micron scaling principles to device fabrication involves an integration of tool capability and resist process control. In order to achieve the realization of improved CMOS device performance and circuit density, sub-micron ground rules (line width control and overlay) must be satisfied over the full chip. This paper reports on a high performance, fully scaled 0.5 micron CMOS technology developed for VLSI applications. Significant gains in both density and performance at reduced power supply levels are realized over previously reported 1.0 micron technology. The details of the integrated lithography strategy used to achieve these results are presented. © 1988, SPIE.