Large-scale 3-D crossbar arrays offer a path to both high-density storage class memory and novel non-Von Neumann computation. However, such arrays require each non-volatile memory (NVM) element to have its own non-linear access device (AD), which must pass high currents through one or more selected cells yet maintain ultra-low leakage through all other cells. Using circuit-level SPICE simulations, we explore design constraints on crossbar arrays composed of a generic NVM element (+1R) together with the novel AD developed by our group, based on Cu-containing mixed-ionic-electronic-conduction (MIEC) materials. We show that power consumption during write, not read margin, is the most stringent constraint for large 1AD+1R crossbar arrays. As array size grows, in order to keep NVM write power-efficient, the voltage at which the AD 'turns on' must outpace the NVM switching voltage. Failure to achieve this condition causes the total array power, injected into the array to ensure the success of the worst-case single-bit write, to greatly exceed the actual NVM write power. Extensive tolerancing results show that NVM switching current and other AD parameters (subthreshold slope and series resistance) are also important, but not to the same degree as AD and NVM voltage characteristics. We show that scaled MIEC devices (Voltage Margin Vm ∼ 1.54V) can support 1 Mb arrays for NVM switching voltages up to 1.2V, and that stacking two MIEC devices could enable ∼ 2.4V. The impact of Vm variability is quantified - we show that there is minimal degradation in write power and read margin at variabilities (standard deviation in Vm) not very different from those already demonstrated experimentally.