Using circuit-level SPICE simulations, we explore the design constraints on crossbar arrays composed of a nonvolatile memory (NVM) (+1R) and a highly nonlinear Access Device (AD) enabled by Cu-containing Mixed Ionic-Electronic Conduction (MIEC) materials [1-5]. Such ADs must maintain ultra-low leakage through a large number of unselected and partially selected 1AD+1R cells, while delivering high currents to the few cells selected for either read or write. We show that power consumption during write, not read margin, is the most stringent constraint for large 1AD+1R crossbar arrays, with NVM switching voltage V NVM and selector voltage margin Vm being much more critical than write current. We show that scaled MIEC devices (Vm ∼ 1.54V ) can support 1Mb arrays for VNVM up to 1.2V. Stacking two MIEC devices enables VNVM ∼ 2.4V. A 20% improvement in Vm can either enable a 4× increase in array size or counteract a 5× increase in interconnect line resistance. © 2014 IEEE.