Etch patterning for advanced devices

Abstract

Recent trend in CMOS technology showed migration towards new device structures. In order to reduce leakage at very small dimension, FINFET has been incorporated into the roadmap. This introduces new challenges on etch patterning due to topography. FINFET gate etch and spacer etch are two of the most challenging steps. For gate last flow, the dummy gate etch is very similar to planar polysilicon gate etch. Selectivity > 1:100 can be easily achieved between polysilicon and silicon dioxide. However, for gate first flow, the gate stack consists of a-Si/TiN/HfO<inf>2</inf> on FINFET topography, which makes gate etch very challenging. Significant over etch is needed to clear the gate materials from FIN side wall, so very high selectivity is needed between multiple etch materials. Nanowire represents the next evolution from FINFET where the gate now surrounds the channel. To overcome the etch challenges, one structure has been demonstrated utilizing a non conventional gate etch process to remove the gate material from under the nanowire [3]. New materials are also being proposed to replace silicon such as SiGe [5] and III-V [6]. For both materials, high selectivity and low damage gate etch and spacer etch are required. For III-V InGaAs MOSFET, the material is even more prone to damage than SiGe. EarlyMOSFET work has always relied on low damage gate definition such as wet etch or lift-off. We have demonstrated that similar performance can be achieved with anisotropic low damage RIE gate etch.