With a continuous focus to maximize computational performance by optimizing package size and reducing fabrication costs, this paper presents the most recent advances on the technology of DBHi (Direct Bonded Heterogeneous Integration) packages as a chiplet packaging technology. The optimizations of DBHi are realized by decreasing the bridge chip thickness from 200 µm to 60 µm and using copper pillars for interconnect, thus enabling the use of standard laminates. The bridge chip that links two main chips features exceptionally fine pitch interconnects (30-75 µm) with the help of µC4 providing flexibility in laminate signal routing by eliminating the cavity in the laminate. The assembly method of the sub-assemblies (2 main chips joined to a silicon bridge) has been optimized to achieve robust and reliable joints, the silicon bridge and the main dies are subjected to a preliminary preparation which involves the positioning of the sub-assemblies with TCB (thermocompression bonding) and reflow process for optimal solder joints. This process is achieved without the use of handlers for the bridge die. This paper also documents a comprehensive FEM model describing the effect of bridge thickness, presence of laminate recess and C4 height on package stress.