Erich P. Stuntebeck, John S. Davis II, et al.
HotMobile 2008
A 'System on a Chip' is described, which integrates 16 Mbits of DRAM, digital logic, SRAM, three PLLs, and a triple video Digital-to-analog converter in a 0.5 micron CMOS DRAM process. Application Specific Integrated Circuit (ASIC) techniques are employed, using multiple DRAM macros with Built-in Self Test (BIST), full Level-Sensitive Scan Design (LSSD) logic, and externally accessible analog circuitry. Issues regarding functional debugging, DRAM macro isolation and low cost manufacturing test using only a logic tester are described.
Erich P. Stuntebeck, John S. Davis II, et al.
HotMobile 2008
Raymond Wu, Jie Lu
ITA Conference 2007
Pradip Bose
VTS 1998
Ehud Altman, Kenneth R. Brown, et al.
PRX Quantum