For the thermal management of a threedimensional (3D) chip stack, cooling from the bottom side of chips (in other words, from the laminate (substrate) side of chips), in addition to conventional cooling from the top surface of chips, is proposed. For cooling from the bottom side of chips, it is essential to consider the trade off among thermal, electrical and mechanical performance. Firstly, the thermal resistance reduction of a laminate (substrate) is evaluated, and the effect of high thermal conductivity insulator is simulated, in addition to thermal vias. Secondly, locating a graphite sheet in the joint (interconnection) layer between a bottom chip and a laminate is proposed. When a graphite sheet is connected to a lid (heat spreader), it is simulated how much heat density can be managed by this cooling structure. Also, when a graphite sheet is used to effectively conduct the hot spot heat to large area of a laminate to accommodate various electrical and thermal via locations, its effect to spread the hot spot heat is simulated.