Benchmarking study on the thermal management landscape for 3D ICS: from back-side to volumetric heat removal
An overview of the thermal management landscape with focus on heat dissipation from 3D chip stacks is provided in this study. Evolutionary and revolutionary topologies, such as single-side, dual-side and, finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W. The thermal budget of 50 K can be maintained by three topologies, namely, 1) dual-side cooling, implemented by a thermally active interposer, 2) interlayer cooling with 4-port fluid delivery and drainage at 100 kPa pressure drop, and 3) a hybrid approach combining interlayer with embedded back-side cooling. Of all the heat-removal concepts, interlayer cooling is the only approach that scales with the number of dies in the chip stack and hence, enables extreme 3D integration. However, the required size of the microchannels competes with the requirement of low TSV heights and pitches. A scaling study was performed to derive the TSV pitch that is compatible with cooling channels to dissipate 150 W/cm2 per tier. An active IC area of 4 cm2 was considered, which had to be implemented on the varying tier count in the stack. A cuboid form factor of 2 mm × 4 mm × 2.55 mm results from a die count of 50. The resulting microchannels of 2 mm length allow small hydraulic diameters and thus a very high TSV density of 1837 1/mm2. The accumulated heat flux and the volumetric power dissipation are as high as 7.5 kW/cm2 and 29kW/cm3, respectively.