Analyzing path delays for accelerated testing of logic chips

Abstract

We develop a test methodology utilizing the critical path delay to monitor and predict the degradation of circuits during a ramp voltage stress (RVS). Stress is applied by looping functional patterns during RVS. Our results demonstrate that the degradation behavior of a functional circuit can be characterized and analyzed with RVS in a manner similar to that developed for a single transistor. This alternative fast test lends itself to in-line testing with reduced times and small sample numbers.